Field of the Invention
The present invention generally relates to program execution preemption and more specifically to instruction level execution preemption.
Description of the Related Art
Preemption is a mechanism to time-slice a processor between multiple different applications. When multiple different applications need to use the processor simultaneously, one way to achieve forward progress on all the applications is to run each application for a short time-slice on the processor. Conventionally, time slicing requires that the processor pipeline be completely drained and when the processor is idle, a different application is switched in to be executed by the processor pipeline. This mechanism for time slicing has been referred to as “wait for idle” preemption and the mechanism does not work well when the processor takes a long time to drain the work that is running on the processor pipeline. For example, consider a very long running graphics shader program, or in the worst case, a shader program with an infinite loop. To be able to time slice between different applications, the amount of time needed to idle execution of each application should be limited so that long running applications do not effectively reduce the time slice available for other applications.
Another mechanism that has been considered to implement preemption, is to stall or freeze the processor and then store the contents of all the registers and pipeline flip-flops within the processor and later restore the contents of all of the registers and pipeline flip-flops within the processor. Storing and restoring the contents of all of the registers and pipeline flip-flops typically results in a very large amount of state to be saved and restored. The time needed to store and restore the state reduces the time available for executing each of the applications during the time slices.
Accordingly, what is needed in the art is a system and method for execution preemption that either does not require storing the entire state of an application when the application is preempted or does not require waiting for a processing pipeline to become idle to preempt the application.